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Five-Day IEP on ASIC Design Successfully Concluded!

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The Department of Electronics and Communication Engineering (ECE), Cambridge Institute of Technology (CIT), successfully organized a Five-Day Instruction Enhancement Program from 23rd to 27th February 2026 on “ASIC Design Flow Using SCL 180nm Technology,” featuring an in-depth case study on a Dual 8-Point FFT Processor with Bus Interfaces. Conducted under the aegis of CCCIR (Centre for Collaborative and Corporate Industry Relations) and supported by the Ministry of Electronics and Information Technology (MeitY), Government of India, the Chips to Startup (C2S) Programme, and the Centre for Development of Advanced Computing (C-DAC), the program was designed to strengthen academic expertise and practical competency in VLSI and ASIC design. The sessions provided comprehensive exposure to the complete ASIC design lifecycle, including system specification, RTL design, simulation, synthesis, timing analysis, physical design, verification, and layout validation using SCL 180nm technology, one of India’s significant semiconductor fabrication platforms. The featured case study enabled participants to understand the architectural design and integration of a high-performance Dual 8-Point FFT Processor with bus interfaces, offering valuable insights into real-world digital signal processing implementations and SoC integration methodologies. The inaugural session was graced by Dr. S. D. Sudarsan, Executive Director, C-DAC Bengaluru, who highlighted the rapid growth of India’s semiconductor ecosystem, the strategic importance of indigenous chip design innovation, and the need for academia to actively contribute to the nation’s semiconductor self-reliance under initiatives such as Make in India and C2S. The program brought together faculty members and students for immersive, hands-on learning experiences, fostering deeper technical understanding, research orientation, and industry readiness in advanced semiconductor technologies. Guided by the visionary leadership of the Cambridge Group of Institutions and meticulously organized by the ECE department team, the program emerged as a resounding success, reinforcing CIT’s commitment to excellence in technical education, industry collaboration, and nation-building through semiconductor innovation.

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Dr. G. Indumathi

Principal, Cambridge Institute of Technology

  • Ph.D. completed during 2012, Dr. M.G.R University Chennai
  • M.Tech Industrial Electronics from SJCE Mysore under VTU in the year 2003
  • B.E. Electronics and Communication , SJCE Mysore , Mysore University in the year 1987

“Technical education is not learning of the facts, but the training of the Mind to think”

                                                                                                                      — Albert Einstein

Cambridge Institute of Technology focuses on imparting quality education to all. We provide an opportunity to all our students to develop the qualities of global professionals. An academic platform through standardized teaching learning processes assist the students towards achieving academic excellence. At Cambridge  Institute of Technology, the students are trained on emerging technologies through Industry collaborative programmes, Real time projects and Internship opportunities through Industry sponsored labs, participate in research activities in advanced research labs. A start up ecosystem is established at the Institute for students and faculty with mentoring, training and infrastructure support to inculcate the start up culture among the young minds. Students have ample opportunities to participate in sports and extra curricular activities. Technical competencies through various clubs at the Departments. Our goal is to develop our students as technocrats who can contribute  to the society and build a sustainable eco system.